Part 1:

A) Create and simulate the following circuit (aka ring oscillator) in SPICE for AMIS 1.5 micron process. Measure oscillation frequencies, low to high response times (tpLH), and high to low response times (tpHL) by varying the load capacitors (C1-C5) for Vdd=3.3V (make sure that 10tp>> tf + tr ). Calculate the Propagation delays. Plot the load capacitor as a function of propagation delay.

B) In the previous simulation, the parasitic capacitances were set to zero. In order to see their effect on your circuit, repeat the simulation after setting AD, AS, PD, and PS values.  You can calculate these parameters by knowing that Lsp=Lsn=Ldn=Ldp= 8u, Wn=3u, and Wp=6u.

C)  Measure the unloaded circuit's oscillation frequency, low to high response time, and high to low response time at Vdd of 2, 3, 4, and 5 V. From your results calculate the average propagation delay for the inverter gate.


D) Use minimum size transistors to compare delays of two 63 gate ring oscillators,   IBM 0.25 micron versus AMIS 1.50 micron.

• SPICE Models
• AMIS 0.5 um n-well process parameters (MOSIS test results)
• Pspice Libraries (model, sch) Orbit 2.0
• Note: One of the inverters in the ring oscillator can be replaced with a NOR gate. This will insure that the circuit does not oscillate at a multiple of the fundamental frequency by allowing the second input to the NOR gate for oscillation initialization.


©2005 Reza Nekovei