Texas A&M University--Kingsville
Department of Electrical Engineering and Computer Science
Principles of CMOS VLSI
ASSIGNMENT 2: RING OSCILLATOR AND PROPAGATION DELAY
Objective: In this Assignment you will get familiar
with SPICE Models and the CMOS inverter load characteristics.
A) Create and simulate the following circuit (aka ring oscillator)
in SPICE for AMIS 1.5 micron process. Measure oscillation frequencies,
low to high response times (tpLH),
and high to low response times (tpHL)
by varying the load capacitors (C1-C5) for Vdd=3.3V (make sure that 10tp>>
tf + tr ). Calculate the
delays. Plot the load capacitor as a function of propagation delay.
B) In the previous simulation, the parasitic capacitances were set
to zero. In order to see their effect on your circuit, repeat the
after setting AD, AS, PD, and PS values. You can calculate these
parameters by knowing that Lsp=Lsn=Ldn=Ldp=
8u, Wn=3u, and Wp=6u.
C) Measure the unloaded circuit's oscillation frequency, low
high response time, and high to low response time at Vdd of 2, 3, 4,
and 5 V. From your results calculate the average propagation delay for
D) Use minimum size transistors to compare delays of two 63 gate
IBM 0.25 micron versus
AMIS 1.50 micron.
AMIS 0.5 um n-well process parameters (MOSIS
Pspice Libraries (model,
Note: One of the
the ring oscillator can be replaced with a NOR gate. This will insure
the circuit does not oscillate at a multiple of the fundamental
by allowing the second input to the NOR gate for oscillation
©2005 Reza Nekovei