Texas A&M University--Kingsville
Department of Electrical Engineering and Computer Science
Principles of CMOS VLSI
ASSIGNMENT 3: PERFORMANCE AND LOGIC GATE DESIGN
Objective: Learning to design logic gates
with considerations for their performance, and to use HSPICE for
creating hierarchical designs. These techniques
are essential for top-down and bottom-up design approaches.
Design and simulate an eight input NAND gate in the following two ways.
First, create a large gate using 16 transistors (8 nmos and 8 pmos) and
measure its rise and fall times.
Next, create the eight input NAND gate by cascading smaller two input
and NOR gates together (using 28 transistors, 2 pmos and 2 nmos per
Verify the circuit and measure its rise and fall times.
Compare the two designs for various load values.
Which design has a better performance and why?
Is the performance improvement better over the rise time or the fall
- Use the MOSIS AMI 0.5u BSIM3 model.
- Keep the W/L ratios constant between the two designs.
- Set all the parasitics.
- Set CL to 0.2pf and Vdd
©2003 Reza Nekovei