Objective:  Understanding the effects of transistor sizing and "self_loading" on system performance, especially for designs with a large fan-in.

Procedure:

 Design the following function:
 

F = (A.B+C.D+E)'

• Simulate the circuit and measure the fall and rise times for minimum size transistors when CL=0.2pF.
• Change transistor sizes to achieve maximum delay tp=tpHL=tpLH<3ns for CL=0.2pF.
• Keep widening the devices until they start showing the "self_loading" effect.

List of SPICE MOSFET model parameter names.

©2005 Reza Nekovei