EEEN 5330

Rapid implementation of very large scale digital integrated circuits. 

1.5 micron technology pads for Magic
VHDL Handout
ModelSim Handout
Related Links

VHDL/ASIC Laboratory

Topics covered:

• VHDL Modeling
• ASIC Cell Library Design
• CPLD/FPGA Rapid Prototyping 
• Logical Effort

Assignments:

Projects

• VHDL Stucture: modeling and Simulation(Due: January 31)
• Simulation and Synthesis (Due: March 2)
• Cell Design and Modeling (Due: March 23)
• Sample MSU VHDL cell model
• Sample Cell Specification Pages (ADK)
• ASIC Cell based System Design and Simulation (Due:  March 23)
• Automated Synthesis (CPLD/FPGA based Design) (Due: April 22)
• FIR design for FPGA; Actel application note [PDF]
• Information on Altera UP1 board 
• Design Optimization and Testing 
• Future of Semiconductor Technology:
• Shrinking Transistors (April 22)
• IC Design  (April 22)
• Ultralight Lithography  (April 22)
• Electron Projection (April 24)
• IC Packaging (April 24)
• Testing (April 24)

Homeworks

• VHDL Simulation
• Introduction to Viewlogic/ModelSim and VHDL (Feb. 1)
• VHDL structure for Thursday Feb. 2 class (new) 
• Intel Internship
• Dealy Modeling, Attributes (Feb. 11)

• Generate (Feb: 20)
• Test Bench Design (Feb. 22)
• VHDL Type Conversion Handout
• Use of Generics (Mar. 4)
• Clock modeling (Mar. 6)
• Subprograms (Mar. 15)
• FSM Design (Mar. 30)
• Synthesis (Apr. 22)
• Design Optimization with Logical Effort
• Gate Effort; Cells (Apr. 8)
• Path Effort (Apr. 15)

• Exam 1: February 9
• Exam 2: March 23
• Exam 3: May 5
• Final Project Due 9:00 AM Friday Apil 28 (Updated)

Location: Engineering Complex, Room 275
Time: 11:00 -12:15 p.m. 

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